1. Field of the Invention
The present disclosed system relates to field-programmable gate arrays, and more particularly, to freeway architectures in field-programmable gate arrays.
2. Description of the Related Art
A field programmable gate array is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the field programmable gate array. A cell may also contain at least one flip-flop. Some types of logic cells found in field programmable gate arrays are those based on multiplexers and those based on programmable read-only memory (PROM) table-lookup memories. Erasable field programmable gate arrays can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
Field programmable gate arrays typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuits and interconnects of the field programmable gate array are customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, a field programmable gate array can perform many different functions. Once a specific configuration of a field programmable gate array has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in a field programmable gate array can be implemented in various technologies, such as ONO antifuse, M-M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. Field programmable gate arrays that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of a field programmable gate array can be reprogrammed repeatedly. In this scenario, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS"" source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, the switch can be turned on or off and thus point A and B are either connected or disconnected. Thus, the ability to program these switches provides for a very flexible device.
Field programmable gate arrays can store the program that determines the circuit to be implemented in a RAM or PROM on the field programmable gate array chip. The pattern of the data in this configuration memory (xe2x80x9cCMxe2x80x9d) determines the cells"" functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of field programmable gate array can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
In general, a field programmable gate array is one type of Programmable Logic Device (PLD), i.e., a device that contains many gates or other general-purpose cells whose interconnections can be configured or xe2x80x9cprogrammedxe2x80x9d to implement any desired combinational or sequential function. As its name implies, a field programmable gate array is xe2x80x9cfield-programmablexe2x80x9d, meaning that the device is generally programmed by designers or end users xe2x80x9cin the fieldxe2x80x9d via small, low-cost programming units. This is in contrast to mask programmable devices which require special steps in the IC chip-manufacturing process.
A field-programming unit typically uses design software to program the field programmable gate array. The design software compiles a specific user design, i.e., a specific configuration of the programmable switches desired by the end-user, into field programmable gate array configuration data. The design software assembles the configuration data into a bit stream, e.g., a stream of ones and zeros, that is fed into the field programmable gate array and used to program the configuration memories for the programmable switches or program the shift registers for anti-fuse type switches. The bit stream creates the pattern of the data in the configuration memory CM that determines whether each memory cell stores a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. Each stored bit the CM controls whether its associated transistor switch is turned on or off. End users typically use design software to test different designs and run simulations for field programmable gate arrays.
When a field programmable gate array that has been programmed to perform one specific function is compared to an Application Specific Integrated Circuit (ASIC) that has been designed and manufactured to perform that same specific function, the field programmable gate array will necessarily be a larger device than the ASIC. This is because field programmable gate arrays are very flexible devices that are capable of implementing many different functions, and as such, they include a large amount of excess circuitry that is either not used or could be replaced with hard-wired connections when performing one specific function. Such excess circuitry generally includes the numerous programmable transistor switches and corresponding memory cells that are not used in implementing the one specific function, the memory cells inside of functional groups, and the field programmable gate array programming circuitry. This excess circuitry is typically eliminated in the design of an ASIC which makes the ASIC a smaller device. An ASIC, on the other hand, is not a flexible device. Once an ASIC has been designed and manufactured it cannot be reconfigured to perform a different function like is possible with a field programmable gate array.
Designers of field programmable gate arrays (as well as other PLDs) often provide their circuit designs to IC manufacturers who typically manufacture the field programmable gate arrays in two different ways. First, a field programmable gate array design may be manufactured as its own chip with no other devices being included in the IC package. Second, a field programmable gate array design may be embedded into a larger IC. An example of such a larger IC is a system on a chip (SOC) that includes the embedded field programmable gate array as well as several other components. The several other components may include, for example, a microprocessor, memory, arithmetic logic unit (ALU), state machine, etc. In this scenario the embedded field programmable gate array may be only a small part of the whole SOC.
The disclosed system relates to a freeway routing system for a field programmable gate array. The field programmable gate array comprises an array of field programmable gate array tiles. Each tile comprises: a plurality of functional groups arranged in rows and columns; a plurality of interface groups arranged such that one interface group is positioned at each end of each row and column, each of the interface groups comprising a set of freeway input and output ports; a freeway set of routing conductors configured to transfer signals to the freeway input ports and from the output ports of the interface groups in each of the field programmable gate array tiles. The freeway set of routing conductors comprises: a plurality of vertical conductors that form intersections with a plurality of horizontal conductors; and programmable bidirectional three state interconnect elements located at the intersections.
The disclosed system also relates to a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises: a two by two array of field programmable gate array tiles. Each tile comprises: a plurality of functional groups arranged in rows and columns; a plurality of interface groups surrounding the plurality of functional groups such that one interface group is positioned at each end of each row and column, and wherein N interface groups are positioned along a vertical inner edge of the tile and N interface groups are positioned along a horizontal inner edge of the tile, and wherein each of the interface groups along the vertical inner edge and the horizontal inner edge comprise a set of fast-freeway input and output ports; a first group of N fast-freeway routing conductors, wherein each of the first through Nth routing conductors of the first group couples the first through Nth interface groups along a first tile""s vertical inner edge to the first through Nth interface groups along a second tile""s vertical inner edge, to the first through Nth interface groups along the second tile""s horizontal inner edge, to the first through Nth interface groups along the third tile""s horizontal inner edge, respectively; a second group of N fast-freeway routing conductors, wherein each of the first through Nth routing conductors of the second group couples the first through Nth interface groups along a second tile""s vertical inner edge to the first through Nth interface groups along a second tile""s horizontal inner edge, to the first through Nth interface groups along the third tile""s horizontal inner edge, to the first through Nth interface groups along the third tile""s vertical inner edge, respectively; a third group of N fast-freeway routing conductors, wherein each of the first through Nth routing conductors of the third group couples the first through Nth interface groups along a second tile""s horizontal inner edge to the first through Nth interface groups along a third tile""s horizontal inner edge, to the first through Nth interface groups along the third tile""s vertical inner edge, to the first through Nth interface groups along the fourth tile""s vertical inner edge, respectively; and a fourth group of N fast-freeway routing conductors, wherein each of the first through Nth routing conductors of the fourth group couples the first through Nth interface groups along a third tile""s vertical inner edge to the first through Nth interface groups along a fourth tile""s vertical inner edge, to the first through Nth interface groups along the fourth tile""s horizontal inner edge, to the first through Nth interface groups along the first tile""s horizontal inner edge, respectively.
A better understanding of the features and advantages of the present disclosed system will be obtained by reference to the following detailed description of the disclosed system and accompanying drawings which set forth an illustrative embodiment in which the principles of the disclosed system are utilized.